I've been doing all my projects involving an FPGAs with Verilog, since thats the HDL I was taught in school but the thing is I've noticed virtually every project I see online is written in VHDL,
for anyone who's had experience with both is it just a better language for DIY projects? would it be worth my time to learn VHDL and use that instead?
>>917139
Its pretty much the same thing. CompEng here, I was taught VHDL in a Digital Systems class that was messing around with FPGAs but in another class we used verilog for something and I remember its pretty much the same, don't worry about that. Use whatever.
>>917145
I still wonder why ever example projects I come across is written in VHDL
From my understanding Verilog is more popular in the US and VHDL is more popular everywhere else. I think VHDL is also more appropriate for scaling when producing ASIC, but I'm definitely no expert. The thing I hate about VHDL is that you have to change everything in about 3 or more places everytime you change something.
>>917160
in my VHDL class, it seemed to depend on peoples google search stuff of weither they got verilog or VHDL. I have always found VHDL examples.
Verilog is what is used nowadays, the reason why you found code in VHDL is because it was written long time ago
>>917331
Altera shill get out.
>>917331
>being this retarded
>>917139
If you can do Verilog, you can do VHDL. It's the same thought process.
Just find documentation so you can look up the functions and syntax.
Verilog is definitely more popular in the US but the places I've worked have been VHDL. The tools handle both anyway, though VHDL seems to be a second-class citizen at times.
Personally I like VHDL better than Verilog because for hardware it's preferable to define exactly what's going on even if it's wordier. Verilog has some stupid stuff like regs, but SystemVerilog fixes that. Anyway as long as you're proficient in one you can learn the others.
