RISC, CISC, VLIW, or EPIC.
Which is best and why?
What are some other options to explore?
>>55220320
CISC any day for just general pourpose aplications.
CISC + RISC coprocessing for high volume calculations
RISC for embeded devices
It's really only comes down to whatever you want to learn and for what you want to develop for.
Sorry this isn't a shitty bait thread that gets 300 replies in 30 minutes.
Bumping with bait.
>>55220338
What makes cisc better? Isn't modern x86 just risc with an x86 interpreter?
I thought this might be more interesting to /g/...
>>55220339
>>55220605
delete this
A modern CISC: Orthogonal, compiler-friendly uarch with many specialty instructions and tagged memory.
>>55220623
Bump
>>55220320
R I S C
I
S
C
but really everything has its uses, its like comparing a sedan to an suv
>>55220349
Because CISC has more available instructions, it means that it can do more stuff "out of the box" as it were so more shit can be compiled simply, I'd that makes sense.
>>55220349
Modern ARM chips decode instructions into micro-ops for re-ordering too.
So what makes RISC better?
>>55220980
But doesn't cisc need to go through more instructions to get the job done? Or something like that
>>55221823
Exact opposite. CISC one instruction to load a register from memory, add another register to it, and then store it back in memory. On most RISC that's at least 3 instructions.
Modern CISC will decode that one instruction to at least 3 micro-operations so it really doesn't mean anything.
>>55221870
So what's the disadvantage? Power consumption?
>>55221877
The real disadvantage is that the instruction decoder is (usually) more complex and larger than a RISC decoder. That's some wasted die space and maybe some power draw.
>>55221996
And I'd assume assembly is harder to learn?
Personally I find it fascinating how Modern ARM processors are starting to overtake older core 2 duos. I know they're old, but the power gap for that level of performance is immense.
>>55222030
Also Intel atoms.
Iirc, bay trail was roughly as fast as an e7200 or e7400. Of course, these processors have more cores than the core 2 duos, but they're also consuming less than 5% the energy.
>>55220339
>>55220605
>>55220695
Wrong board.
>>55222061
The 10W Core 2 SU7300 performs about as well as the 7.5W Bay Trail N2840. The bay trail has far fewer support chips to deal with though.
>>55220320
MIPS is where it's at so RISC. Needing more instructions is a meme
>>55222098
processors aren't technology?
>>55220320
Depends on usage.
For desktop/PC/workstation/mobile where you have wide range of CPUs that all need to perform well with available binary application, an architecture with stable ISA and out of order engines that perform well without targeted compiler optimizing - definitely architecture that is CISC on the outside like x86. With the current architectures, it is not oldschool CISC anymore though.
VLIW can be good for specific usages, but needs recompiling and optimization all the time.
RISCs today usually are close to CISCs but they waste memory, bw and cache space.
The rule of thumb is generally that ISAs don't matter. Microarchitectures of the cores do.
Fat out of order Power and x86 chips could be very similarly performing and the winner will be decided by microarchitecture and manufacturing node. (Assuming one of them doesn't lack crucial ISA parts like SIMD).
>>55220320
CISC is the best
RISC is overly complicated and kind of hard to follow if you're used to CISC
t. Hobbyist learning to program microcontrollers
