Thread replies: 7
Thread images: 1
Anonymous
2016-03-21 17:53:58 Post No. 53609435
[Report]
Image search:
[Google]
Anonymous
2016-03-21 17:53:58
Post No. 53609435
[Report]
is this JKFF?
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:38 03/20/2016
-- Design Name:
-- Module Name: JKFlipFlopModule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JKFlipFlopModule is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
C : in STD_LOGIC;
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC);
end JKFlipFlopModule;
architecture Behavioral of JKFlipFlopModule is
begin
Q <= ((Qn nor K) and (J and C));
Qn <=((Q nor J) and (K and C));
end Behavioral;
