What's up bitchs?
Anyone know about FPGA?
I'm trying to simulate an JK flip-flop module on Xilinx design suite using this two command lines but receiving errors
Q <= ((J nand J) nand (J nand J) nand (C nand C)) nand Qn;
Qn <= ((K nand K) nand (K nand K) nand (C nand C)) nand Q;
What am i doing wrong?
>>53589345
Post errors.
>>53589382
i remember quartus gave a 100+ errors even when your code worked. good times.
>>53589345
>What am i doing wrong?
everything
>>53589345
It's been a long time since I've worked with FPGAs but something about your code looks wrong.
post full vhdl code, from the import statements to the end of your behavioral
Think i fix it :
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:38 03/20/2016
-- Design Name:
-- Module Name: JKFlipFlopModule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JKFlipFlopModule is
Port ( J : in STD_LOGIC;
K : in STD_LOGIC;
R : in STD_LOGIC;
S : in STD_LOGIC;
C : in STD_LOGIC;
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC);
end JKFlipFlopModule;
architecture Behavioral of JKFlipFlopModule is
begin
Q <= ((J nand S) nand (C)) nand Qn;
Qn <= ((K nand R) nand (C)) nand Q;
end Behavioral;
