So I have an idea involving audio equipment with a lot of digital signal processing. I want to use FPGAs to do most of the math. I want to implement things like adders, multipliers, frequency filters, discrete Fourier transforms, etc...
I'll give you the tl;dr upfront: what is the the best hardware description language to learn to code these types of things? Which is the most supported hardware description language when it comes to the tools needed to transform the code in to whatever signal I need to send to the FPGA to program it? Wide support is really my biggest concern.
non tl;dr;
I took a combination digital logic and a sequential logic class during the three years I pursued an electrical engineering degree. I remember my book covered hardware description languages but we never went over them in class. The two names I remember are Verilog and VHDL. Have either of these become the "standard" language? Has any other language become the defacto standard? Please suggest languages and pros and cons associated with each language. Also please explain what kind of work flow I'll be dealing with in order to change the code in to the signal I need to send to the chip to make it work like I want it to. Is it just a case of choosing a supported language and putting the code in a tool provided by the chip manufacturer or are there intermediate steps?
Here are my priorities for suggesting HDLs in order of importance
1. Wide support different FPGAs
2. Bit level control (I assume this is possible in all HDLs but I leave room for me to be surprised and disappointed)
3. Likely to find use for this language in finding work or using it at work
4.expressive and powerful
(so a defacto standard would be big in satisfying 1-4)
=====================
5. Ease of use
6. I'm interested in languages that are close to C in syntax. To get an idea of what I consider close I consider C, C++, C#, python, and java as C like.
7. Easy to learn.
I'm pretty sure the only HDLs used are still VHDL and Verilog
>>52183725
Do you know anything about the pros and cons of each?
>>52184077
just use VHDL
>>52184077
The only pros and cons stem from the IDEs available for each.
In my limited experience, VHDL seems to have better tools for hardware prototyping, but there are some VHDL to Verilog tools so
¯\_(ツ)_/¯
I've done all the things you have mentioned in VHDL. There is a really great FFT/IFFT open source code on freecores called versatile_fft Most of the other things can be accomplished with Xilinux IP (free in ISE). Filters coefficients are easy to generate with octave. Note that you will need more than a low-end FPGA. I used high-end Spartan 6 and was running out of resources. Would recommend at least Artix 7 series.
>>52184202
Do you know anything about doing encryption and using them to mine cryptocurrencies?
>>52184339
Never played with cryptocurrencies on FPGA, but there are AES implementations on freecores as well. I think I downloaded and played around with testbench on one, but didn't verify or use in a design yet. From what I recall, the throughput rates were incredible on the one I checked out due to pipelining.
>>52183679
learn verilog or VHDL, then if you want you should learn HardCaml, which is a DSL in ocaml that compiles down to Verilog or VHDL. It's pretty great desu.
Here is a little tidbit that I'll share in case someone reading this is interested in FFT and is confused. The input to an FFT can be real with imaginary input as all zeros. In this case, the output will be mirrored and you can throw out the second half (channel/bandwidth) of the output. If you actually feed the FFT complex data, then you can use the full bandwidth of the output. This caused me some confusion in the beginning, so hoping to help someone else out.
>>52184382
Does Xilinx or any other company send out free samples of powerful FPGAs? I remember I used to have stacks of ARM 5,7, and I think 9 chips along with some atmel and microchip microcontrollers. I had $100 ADCs that I never used but ordered just because I could.
I'm definitely going to free cores. I remember back when I was playing with GPU mining coming across a forum post that said there were some people running FPGA bitcoin miners that would reprogram their FPGAs to crack wireless network passwords for money. This type of thing interests me
Not so much wireless networks but cell phone transmissions. I remember reading about a hacker group that was planning to release a cipher text only algorithm for decrypting digital voice over cell phone networks. They got served with a cease and desist order at the hacker conference they were going to demonstrate it. Supposedly the info is out there but they decided not to demonstrate it.
I don't know if they've changed how they do voice encryption on the cells but I'm wondering if this would be useful for that if they've changed it. Also decrypting the new police radios with voice encryption sounds fun.
I'm browsing the Xilinx site. I came across a 64 speaker surround system that uses beam forming algorithms. Now that I think about it this would be the perfect tech for powering a beam forming antenna array. I'm an amateur radio operator and I've worked with USRPs doing software radio. They had a FPGA on board but the code for them was handled by gnu radio and all I did was set the decimation and low pass filter levels that the fpga did on the samples before it sent it to a usb chip. That was all done in python.
Verilog is looking good with a free software toolchain for for some cheap fpgas (about $25).
Checkout:
https://media.ccc.de/v/32c3-7139-a_free_and_open_source_verilog-to-bitstream_flow_for_ice40_fpgas
http://www.clifford.at/icestorm/
>>52184581
Ahh you're helping my memory. I remember every signal with only a real component had negative and positive frequency components. Something like
cos(1000*pi*t) = (cos(1000*pi*t)+jsin(1000*pi*t))/2 + (cos(1000*pi*t)-jsin(1000*pi*t))/2
where the first component was the positive and the second negative. Good fun. I've got to find my signals and systems and my digital logic book. I never sold those.
>>52184634
I don't know if you can get free samples, but I kinda doubt it unless you are a big company with big goals for the part. My application was SDR-related and as I mentioned earlier, I wish I would have gone with Artix 7 instead of Spartan 6. I've played with P25 police reception using open-source implementations, but they didn't implement crypto stuff. From my understanding only DEA typically uses it. Which of course implies NSA as well. Obviously FPGA can be used in beam-forming applications, but that is out of my scope for now. The USRP is a really nice looking hardware design, but the FPGA stuff that they offer is hard for me to follow, otherwise I would have probably purchased one to play with.
>>52184764
Does that imply most FPGA products require you to purchase software to target them with a hardware description language? Open source is a plus but cheap is a must.
>>52185207
No, I've only dealt with Xilinx so far, but the environments and IP (FPGA speak for libraries) are free for most general applications. I believe the same is true for Altera and Lattice. When you want something specialized like PCIe, LTE, JESD204, etc then you might have to pay for the "IP".
>>52184847
I'm definitely going to go with the biggest FPGA I can get my hands on for development. I learned that with microcontrollers. I want to sell this and I'll optimize it and try to make it fit on the cheapest chip if I ever get around to selling them. It's going to be fucking awesome. I'm thinking about a 7.1 surround system with a 50 channel equalizer on each channel. Why? because I think I can. I haven't actually looked in to how many components I will need to do filters. Each channel will be triamped so cross over is done before amplification. I'm thinking touch screen interface. I'm going over kill all the way. Something like 192kilosamples per second 24bit ADCs on the inputs. I'll handle data as 32bits internally in the FPGA when do the adding(mixing), and multiplying(volume).
Looking at these transistor sizes they're comparable to core x64 processors. If I could run one adder at 1 Billion 32bit additions per second I could use one adder with a multiplexer on the input and output and reuse that adder for each addition and have like 800 Million additions per second idle or something.
Is it possible to construct digital bandpass filters that keep the phase relationship between the frequencies? Any advice on choosing finite or infinite impulse response filters? Are there any other types of digital filters?
Is P25 regular police trunking?
Also definitely recommend the USRP but I can only speak on USRP 1. You don't have to know shit about FPGAs. I mean it helps it make sense if you know Math happens here but that's all that's necessary. in python you do something like
gnuradio.sink sendShitToTransmitHere = usrp.initialize_transmitter(SLOT_NUMBER, INSTALLED_CARD_TYPE, CENTER_FREQ, DECIMATION_FACTOR);
gnuradio.source receiveShitFromThis = usrp.initialize_receiver(SLOT_NUMBER, INSTALLED_CARD_TYPE, CENTER_FREQ, DECIMATION_FACTOR);
Then the usrp object figures out what code to send the FPGA from that.
>>52185268
So the environment is is what you type in the VHDL and "compile" it to a data stream to send the FPGA to program it and The LPs are premade chunks of VHDL?
>>52185289
I messed up. Actually you would use an interpolation factor for the transmitter initialization but same idea
>>52185360
>So the environment is is what you type in the VHDL and "compile" it to a data stream to send the FPGA to program it and The LPs are premade chunks of VHDL?
Yes, that is essentially the idea. The IP (Not LP) are supplied in such a way that you can interface with them, but you don't get the source code in that case. There are third-party vendors that also supply IP for various things like OFDM 802.11 stuff etc.
Some stuff I found useful getting started:
http://vhdlguru.blogspot.com/
http://www.fpga4fun.com/
https://github.com/freecores (essentially a mirror of opencores)
>>52185562
I'm collecting quite a useful folder full of bookmarks thanks.
It doesn't look like Xilinx does free samples at least through an automated online form. I have had some success, when I was at LSU, telling them "I'm a student and need x because I want to do y." and getting components sent to me.
I'm digging through the digikey product listing. Man some of these chips are listed as 30000. Anyway they list three things I'm interested in. Once is LABs/CLBs which from what I gather from wikipedia is pic related.
The other things are logic elements/cells and gates. I think I know what a gate is but what is a logic element/cell? Are all those gates part of CLBs or are they usable separately?
When it says RAM bits are those separate from the CLBs/LABs? Like regular edge triggered flip flops?
>>52185945
forgot my pic
>>52185945
To be honest, I really don't know what your requirements will be. I am relatively new to this myself and am only reporting what I found out from implementing similar things to your interests at the VHDL level. When combining FFT 1024 bins, Complex Mixer, Spectral magnitude (complex abs), dual FIR filters for I/Q, FM demod (phase detector, loop filter, low-pass filter), DC Offset correction, and can't remember what else off the top, I started to run into limitations with a Spartan 6 LX-25 FPGA if I tried to do much more than this.
