so I'm trying to get my FPGA to display with a monitor via a VGA connection
I've read the timing charts on some guides online but I don't understand what the squiggly part is suppose to represent, any idea?
>>903563
Probably something to do with the fact that the RGB values are not discrete.
>>903568
so the squiggles it whatever analog value I have set up?
>>903583
It's the actual picture you want to display. One squiggle = one line.
>>903563
That diagram looks like sync-on-green. Fuck that shit. Just use separate HSync and VSync lines.
VGA uses timing intended to drive a CRT. When HSync is low the electron gun resets to the left of the screen, and when high sweeps towards the right at a fixed rate. Likewise, when VSync is low the electron gun resets to the top of the screen, and when high sweeps towards the bottom at a fixed rate, much slower than the horizontal sweep rate. R, G, and B are just 0V to 7V analog signals, but are expected to be 0V when either HSync or VSync is low so it doesn't draw a line on the screen when it moves back.
>>903603
D'oh. R, G, and B are 0V to 0.7V, not 7V. Also, HSync and VSync are 5V, but 3.3V should work with most monitors.
so far I got the whole screen to flicker a solid color for an instant every few seconds ,
at least I know its drawing a whole frame before it crashes
could it an incorrect timing for VS cause this?
>>904483
Are you doing the porching correctly? The R,G,B wires should be at ground a little before and a little after the Vsync and Hsync pulses because this is when the electron beam is moving across the monitor to get into position.
You'd think that forgetting about the porching would just result in some ugly diagonal lines, but a lot of monitors treat incorrect porching as an error and turn themselves off or exhibit other strange behavior.
>>904488
this is my simulated testbench since I dont have an oscilloscope
the r array is the input value to color the screen and the red array is the output array that connects 4 poins in a voltage divider to give an analog voltage.
r is set at 0011 or 3hex
I still have the screen crash doing this porching as I understand it , I can tell since attempting to open the menu gets immediately closed .
oddly enough I can get the screen to flicker a solid frame before crashing if I code my counter as:
always@(posedge clk)
begin
if(count<endStage)begin count=count+1;end
if(count==endStage)begin count=count+1;end
if(count>endStage)begin count=0;end
end
but not if I code it as:
always@(posedge clk)
begin
if(count<endStage)
count=count+1;
else
count=0;
end
I can't fathom why that would make a difference.
>>904804
>>904804
In the first example count resets to 0 when it's greater than endStage. In the second example count resets to 0 when it's equal to endStage. First example counts one higher.
It's an FPGA so lines aren't executed sequentially like with a programming languages. This line will make count > endstage:
>if(count==endStage)begin count=count+1;end
, but the next line won't execute until the function is called again on the next clock cycle:
>if(count>endStage)begin count=0;end
ok so I got this to work by having the the hsync value only update on a negative clock edge , upon further inspection I noticed on a positive clock edge it would just randomly spike up and down which would throw off the timing of vsync (since I kept the clock for vsync relative to hsync), that would explain why it could draw one full frame before crashing.
>>903563
Just got a FPGA
Tryin to get it to display!
Goin' to 4chan, post a pic of the porch.
/diy/ it sets in pretty soon I'm syncin'
Doo doo doo lookin' at my black porn.
would it be worth my time to learn VHDL so I can use that instead of verilog?
>>905208
Define worth. One item more in your resume = worth your time?
>>905211
avoiding unforseen problems and errors when coding an fpga,
also I notice a lot of projects for fpga's that ive come across on the internet such as old console emulators and such are coded in VHDL so I figure there must be a good reason for it.
>>905212
Traditional knowledge was that the US used Verilog, Europe VHDL. Don't know if that's still the case. You can also try other languages, like MyHDL or SystemC.
